1. Field of the Invention
The present invention relates to a class D amplifier to be installed in a portable telephone, for example, and more particularly to the class D amplifier of which the power consumption is decreased.
2. Description of the Related Art
Generally a digital amplifier comprises a comparator receiving an audio signal and a triangular wave carrier wave, putting out a PWM (Pulse Width Modulation) signal, and a class D output stage which amplifies the output of the comparator.
In such a digital amplifier, the comparator compares the audio signal and the triangular wave, and generates the PWM signal. The output stage switch is controlled by this PWM signal, and the load unit, such as a speaker, is driven by the output of the class D output stage. The high frequency component is removed by the output LPF (Low Pass Filter) during driving the load unit.
Practically, however, in the digital amplifier, non-linear distortion is generated due to the curvature of the triangular wave, pulse width distortion and power supply voltage variations, so negative feedback is used to improve non-linear distortion. One of such methods negatively feeds back the output of the output stage to the integrating amplifier installed as an integrating circuit in a previous stage of the comparator. The integrating amplifier extracts and amplifies the low frequency component included in the feedback signal of the square wave (PWM wave).
While this separately-excited oscillation type PWM system operates with such incoming triangular waves, there is a self-excited oscillation type PWM digital amplifier which oscillates by itself without incoming external triangular waves so that the output of the integrating amplifier is a triangular wave (e.g. Japanese Unexamined Patent Application Publication No. 2003-115730 (hereafter referred to as “related art”)). In the self-excited oscillation type PWM system, the triangular wave oscillation circuit is unnecessary, and a Schmitt trigger circuit, for example, is used instead of a comparator.
FIG. 5 is a block diagram depicting a conventional self-excited oscillation type class D amplifier. As FIG. 5 shows, the class D amplifier 101 with a differential output (Bridge—Tied Load: BTL) is comprised of a differential signal output unit 102 consisting of the resistors R101-R104 for converting voice signals from the input terminal Sin into differential signals, and the full differential amplifier A101, and each charge balanced class D amplifier at the P-side and N-side receiving the differential signals.
The N-side charge balanced class D amplifier comprises a PWM waveform generation circuit and a feedback circuit. The PWM waveform generation circuit consists of an integrating amplifier 103N consisting of an operation amplifier A102 and a capacitor C101, and a Schmitt trigger circuit 104N consisting of resistors R107-R109 and a comparator COMP 101. The feedback circuit comprises an output buffer B101 and a resistor R111 for negatively feeding back the output of the output buffer B101 to the integrating amplifier 103N. The PWM waveform generation circuit consisting of the integrating amplifier 103N and the Schmitt trigger circuit 104N, is a self-excited oscillation type oscillation circuit which oscillates automatically without providing triangular waves, and the output of the integrating amplifier 103N is a triangular wave.
The Schmitt trigger circuit 104N, at the power supply level is VDD1, has the following two threshold values according to the output LOW or HIGH for determining LOW and HIGH of the input voltage (output of integrating amplifier 103N).VH=Vcom((R107+R109)/R109)VL=(Vcom(R107+R109)−VDD1×R107)/R109The P-side charge balanced class D amplifier is also configured similar to the N-side, and in the Schmitt trigger circuit 104P, has the following two threshold values according to the output LOW or HIGH for determining LOW and HIGH of the input voltage (output of the integrating amplifier 103P).VH=Vcom((R108+R110)/R110)VL=(Vcom(R108+R110)−VDD1×R108)/R110
Now the operation of the conventional class D amplifier will be described. FIG. 6 is a diagram depicting the signal waveform of each node in the class D amplifier 101, where S1 is a voice signal (analog signal) which comes from the input terminal Sin, S2 is an output waveform of the output buffer B102 when the voice signal is a silent signal, S3 is the P-side output waveform when the voice signal of S1 is presented from Sin, S4 is the N-side output waveform when the voice signal of S1 is provided from the input terminal Sin, and S5 is an amplitude applied to the load to be connected to the subsequent stage of the class D amplifier. FIG. 7 shows the relationship of the output voltage of the integrating amplifier (input voltage of the comparator) and the output voltage (Vout) of the output terminal OUTP where the abscissa is time and the ordinate is voltage.
First the case when voice signals are not provided from the input terminal Sin (voice signal=silent signal) will be described. The non-inverting input terminals of the integrating amplifiers 103N and 103P are connected to the reference potential Vcom respectively, and the non-inverting input terminals of the comparators COMP 101 and 102 are connected to the reference potential Vcom respectively. Each charge balanced class D amplifier at the P-side and the N-side operates similarly, so the operation of only the P-side charge balanced class D amplifier will be described below.
In the case when the voice signal is the silent signal, the voltage Vsin of the non-inverting input terminal of the integrating amplifier 103P is Vsin=Vcom. As FIG. 7A shows, if the output voltage Vout of the output terminal OUTP is HIGH (power supply level) (time T1), the output voltage VA of the integrating amplifier 103P drops since the current flows into the capacitor C102 of the integrating amplifier 103P through the resistor R112. If the output VA of the integrating amplifier 103P goes below the threshold level VL of the comparator COMP 102, the output voltage Vout of the output terminal OUTP goes LOW, and current flows out of the integrating amplifier 103P, so the output voltage VA of the integrating amplifier 103P increases. If the output voltage VA of the integrating amplifier 103P exceeds the threshold level VH of the comparator COMP 102, the comparator COMP 102 puts out HIGH, and the output terminal OUTP goes HIGH. Repeating the operations results in oscillation. At this time, the charge amount that flows into the integrating amplifier 103P from the output terminal OUTP via the feedback circuit and the charge amount which flows out from the integrating amplifier 103P to the OUTP side are equal, so the average output level is equal to the non-inverting input level (Vcom) of the integrating amplifier 103P (S2 in FIG. 6).
Now the case when the voice signal is input from the input terminal Sin will be described. According to the voice signal amplitude from the input terminal Sin shown in FIG. 5, the output level (Aop) of the differential amplifier A101 becomes as follows.Aop=(Vsin−Vcom)×R104/(2×R101)
When the level of Aop is higher than the non-inversing level Vcom of the integrating amplifier A103, current flows into the integrating amplifier A103 from Aop. If the output terminal OUTP is HIGH at this time, the current that flows into the integrating amplifier 103P is the sum of the current from Aop and the current from the feedback circuit, thus as time T1 in FIG. 7B shows, the output voltage reaches the threshold level VL of the comparator COMP 102 and the output terminal OUTP goes LOW sooner compared with the case of the silent signal, that is time T1 in FIG. 7A. This means that the width of HIGH has become shorter. If the output terminal OUTP is LOW, on the other hand, the current that flows into the integrating amplifier 103P is the current from the feedback circuit from which the current from Aop is subtracted, therefore compared with the case of the silent signal, the time to reach the threshold level LH of the comparator COMP2 (time T2) becomes longer. This means that the time period of LOW becomes longer.
This is the same for the case when the level of Aop is at the lower level than Vcom, and as FIG. 7C shows, when the output terminal OUTP is HIGH, time T1 is longer since the current that flows into the integrating amplifier 103P is subtracted, and when the output terminal OUTP is LOW, the time T2 is shorter since the current that flows into the integrating amplifier A103 is added. In this way, PWM waveforms, where the duty of the output pulse changes according to the level of Aop, can be generated as shown in S3 and S4 in FIG. 6.
The output waveform which is acquired by filtering this output is as follows.Vout=(Vsin−Vcom)×R104×R112/(2×R101×R106)+Vcom
In other words, the loop from the integrating amplifier 103P at the P-side to the output buffer B102 has inversing amplifiers connected in a series. This is the same for the loop from the integrating amplifier 103N at the N-side to the output buffer B101.
However in the class D amplifier 101 shown in FIG. 5, the power supply voltage of the switching circuit in the output buffers B101 and B102 may fluctuate, and if this power supply voltage fluctuates, the gain fluctuates, therefore in some cases the system becomes unstable. To avoid this, the above mentioned the related art discloses a power amplifier (hereafter class D amplifier), where voltages, after the positive power supply voltage and negative power supply voltage of the switching circuit of the output stage are divided at a predetermined voltage dividing ratio, are switched according to the output of the comparator, and are input to the input end of the comparator.
FIG. 8 is a diagram depicting a major section of the class D amplifier described in the related art. As FIG. 8 shows, the conventional class D amplifier comprises a PWM modulation circuit 133a and a switching circuit 134 for amplifying the PWM signals which are output from the PWM modulation circuit 133a, wherein the PWM signals amplified by the switching circuit 134 are output to the speaker (not illustrated) via the LC filter (not illustrated). The switching circuit 134 comprises an N-type FET (Field Effect Transistor) 145 and a P-type FET 146, which are connected in series.
The PWM modulation circuit 133a comprises an integrating amplifier 139 consisting of a capacitor 136 and an operational amplifier 137, a comparator 140, a resistor 142 disposed between the output of the integrating amplifier 139 and non-inverting input terminal of the comparator 140, and an inverter 186 for inverting the output of the comparator 140. The PWM modulation circuit 133a further comprises a switch 182 for the positive side power supply voltage VPX to be connected to the common terminal via the resistor 181, and the switch 182 switches the two contacts so that the GND or the node P between the non-inverting input terminal of the comparator 140 and the resistor 142 is selected according to the output of the comparator 140. The PWM modulation circuit 133a also comprises a switch 184 for the negative side power supply voltage VMX to be connected to the common terminal via the resistor 183, so that the common terminal switches the two contacts so that the GND or the node P is selected according to the inverting output of the comparator 140.
The switch 182 controls such that the common terminal and the node P are connected when the output of the comparator 140 is HIGH level, and the common terminal and the GND are connected when the output is LOW level. The switch 184 controls such that the common terminal and the node P are connected when the output of the comparator 140 is LOW level, and the common terminal and the GND are connected when the output is HIGH level.
In the conventional class D amplifier configured in this way, the maximum value VP and the minimum value VM of the integrating output (triangular wave), which is input to the input end P of the comparator 140, are in proportion to the power supply voltages VPX and VMX of the switching circuit 134 respectively. As a result, the gain from the node P at the input end side of the comparator 140 to the output end Q of the switching circuit 134 is a constant, as shown in the following Expression (1), which is no relation to the power supply voltage VPX and VMX, therefore the fluctuation of the circuit gain based on the power supply voltages VPX and VMX can be prevented.G=(VPX−VMX)/(VP−VM)  (1)
However as described above, the charge balanced type class D amplifier shown in FIG. 5 has resistance feedback, assuming that the PWM conversion unit comprised of the full differential amplifier 102, integrating amplifiers 103N and 103P and Schmitt trigger circuits 104N and 104P, and the output unit (output buffers B101, B102) are constructed under the same level of the power supply. For a circuit for which low power consumption is demanded, such as a circuit for a portable telephone, only the power supply level for the output buffers B101 and B102 may be increased, while decreasing the power supply level for the other signal conversion sections, so that power consumption is decreased and high amplitude is acquired. In this case, if the configuration based on resistance feedback is used, the average level of output at the silent signal is determined by the non-inverting input level of the integrating amplifiers 103N and 103P, so the GND side clamps and amplitude cannot be sufficient.
Also in the class D amplifier shown in FIG. 8, the gain of the input signal and output signal can be determined by the ratio of the resistance 132 and the resistance 187, but the output at silent signal becomes the same as the non-inverting input level of the integrating amplifier 139, so if the power supply level of the PWM modulation circuit 133a is VDD1 and the power supply level of the switching circuit 134 is VDD2, then the output of the switching circuit 134 cannot be amplified fully to the power supply level with VDD2/2 at the center, and a sufficiently high amplitude cannot be acquired.